Espressif Systems /ESP32-S2 /PMS /PRO_AHB_2

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Interpret as PRO_AHB_2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRO_AHB_RTCSLOW_1_SPLTADDR 0 (PRO_AHB_RTCSLOW_1_L_F)PRO_AHB_RTCSLOW_1_L_F 0 (PRO_AHB_RTCSLOW_1_L_R)PRO_AHB_RTCSLOW_1_L_R 0 (PRO_AHB_RTCSLOW_1_L_W)PRO_AHB_RTCSLOW_1_L_W 0 (PRO_AHB_RTCSLOW_1_H_F)PRO_AHB_RTCSLOW_1_H_F 0 (PRO_AHB_RTCSLOW_1_H_R)PRO_AHB_RTCSLOW_1_H_R 0 (PRO_AHB_RTCSLOW_1_H_W)PRO_AHB_RTCSLOW_1_H_W

Description

PeriBus2 permission control register 2.

Fields

PRO_AHB_RTCSLOW_1_SPLTADDR

Configure the split address of RTCSlow_1 for PeriBus2 access.

PRO_AHB_RTCSLOW_1_L_F

Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 low address region.

PRO_AHB_RTCSLOW_1_L_R

Setting to 1 grants PeriBus2 permission to read RTCSlow_1 low address region.

PRO_AHB_RTCSLOW_1_L_W

Setting to 1 grants PeriBus2 permission to write RTCSlow_1 low address region.

PRO_AHB_RTCSLOW_1_H_F

Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 high address region.

PRO_AHB_RTCSLOW_1_H_R

Setting to 1 grants PeriBus2 permission to read RTCSlow_1 high address region.

PRO_AHB_RTCSLOW_1_H_W

Setting to 1 grants PeriBus2 permission to write RTCSlow_1 high address region.

Links

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